
freertos-link:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400480 <_init>:
  400480:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400484:	910003fd 	mov	x29, sp
  400488:	94000030 	bl	400548 <call_weak_fn>
  40048c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400490:	d65f03c0 	ret

Disassembly of section .plt:

00000000004004a0 <.plt>:
  4004a0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4004a4:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0xfd94>
  4004a8:	f947fe11 	ldr	x17, [x16, #4088]
  4004ac:	913fe210 	add	x16, x16, #0xff8
  4004b0:	d61f0220 	br	x17
  4004b4:	d503201f 	nop
  4004b8:	d503201f 	nop
  4004bc:	d503201f 	nop

00000000004004c0 <__libc_start_main@plt>:
  4004c0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4004c4:	f9400211 	ldr	x17, [x16]
  4004c8:	91000210 	add	x16, x16, #0x0
  4004cc:	d61f0220 	br	x17

00000000004004d0 <__gmon_start__@plt>:
  4004d0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4004d4:	f9400611 	ldr	x17, [x16, #8]
  4004d8:	91002210 	add	x16, x16, #0x8
  4004dc:	d61f0220 	br	x17

00000000004004e0 <abort@plt>:
  4004e0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4004e4:	f9400a11 	ldr	x17, [x16, #16]
  4004e8:	91004210 	add	x16, x16, #0x10
  4004ec:	d61f0220 	br	x17

00000000004004f0 <printf@plt>:
  4004f0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4004f4:	f9400e11 	ldr	x17, [x16, #24]
  4004f8:	91006210 	add	x16, x16, #0x18
  4004fc:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400500 <_start>:
  400500:	d280001d 	mov	x29, #0x0                   	// #0
  400504:	d280001e 	mov	x30, #0x0                   	// #0
  400508:	aa0003e5 	mov	x5, x0
  40050c:	f94003e1 	ldr	x1, [sp]
  400510:	910023e2 	add	x2, sp, #0x8
  400514:	910003e6 	mov	x6, sp
  400518:	580000c0 	ldr	x0, 400530 <_start+0x30>
  40051c:	580000e3 	ldr	x3, 400538 <_start+0x38>
  400520:	58000104 	ldr	x4, 400540 <_start+0x40>
  400524:	97ffffe7 	bl	4004c0 <__libc_start_main@plt>
  400528:	97ffffee 	bl	4004e0 <abort@plt>
  40052c:	00000000 	.inst	0x00000000 ; undefined
  400530:	00400b64 	.word	0x00400b64
  400534:	00000000 	.word	0x00000000
  400538:	00400c28 	.word	0x00400c28
  40053c:	00000000 	.word	0x00000000
  400540:	00400ca8 	.word	0x00400ca8
  400544:	00000000 	.word	0x00000000

0000000000400548 <call_weak_fn>:
  400548:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0xfd94>
  40054c:	f947f000 	ldr	x0, [x0, #4064]
  400550:	b4000040 	cbz	x0, 400558 <call_weak_fn+0x10>
  400554:	17ffffdf 	b	4004d0 <__gmon_start__@plt>
  400558:	d65f03c0 	ret
  40055c:	00000000 	.inst	0x00000000 ; undefined

0000000000400560 <deregister_tm_clones>:
  400560:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  400564:	9100c000 	add	x0, x0, #0x30
  400568:	d0000081 	adrp	x1, 412000 <__libc_start_main@GLIBC_2.17>
  40056c:	9100c021 	add	x1, x1, #0x30
  400570:	eb00003f 	cmp	x1, x0
  400574:	540000a0 	b.eq	400588 <deregister_tm_clones+0x28>  // b.none
  400578:	90000001 	adrp	x1, 400000 <_init-0x480>
  40057c:	f9466421 	ldr	x1, [x1, #3272]
  400580:	b4000041 	cbz	x1, 400588 <deregister_tm_clones+0x28>
  400584:	d61f0020 	br	x1
  400588:	d65f03c0 	ret
  40058c:	d503201f 	nop

0000000000400590 <register_tm_clones>:
  400590:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  400594:	9100c000 	add	x0, x0, #0x30
  400598:	d0000081 	adrp	x1, 412000 <__libc_start_main@GLIBC_2.17>
  40059c:	9100c021 	add	x1, x1, #0x30
  4005a0:	cb000021 	sub	x1, x1, x0
  4005a4:	9343fc21 	asr	x1, x1, #3
  4005a8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4005ac:	9341fc21 	asr	x1, x1, #1
  4005b0:	b40000a1 	cbz	x1, 4005c4 <register_tm_clones+0x34>
  4005b4:	90000002 	adrp	x2, 400000 <_init-0x480>
  4005b8:	f9466842 	ldr	x2, [x2, #3280]
  4005bc:	b4000042 	cbz	x2, 4005c4 <register_tm_clones+0x34>
  4005c0:	d61f0040 	br	x2
  4005c4:	d65f03c0 	ret

00000000004005c8 <__do_global_dtors_aux>:
  4005c8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4005cc:	910003fd 	mov	x29, sp
  4005d0:	f9000bf3 	str	x19, [sp, #16]
  4005d4:	d0000093 	adrp	x19, 412000 <__libc_start_main@GLIBC_2.17>
  4005d8:	3940c260 	ldrb	w0, [x19, #48]
  4005dc:	35000080 	cbnz	w0, 4005ec <__do_global_dtors_aux+0x24>
  4005e0:	97ffffe0 	bl	400560 <deregister_tm_clones>
  4005e4:	52800020 	mov	w0, #0x1                   	// #1
  4005e8:	3900c260 	strb	w0, [x19, #48]
  4005ec:	f9400bf3 	ldr	x19, [sp, #16]
  4005f0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4005f4:	d65f03c0 	ret

00000000004005f8 <frame_dummy>:
  4005f8:	17ffffe6 	b	400590 <register_tm_clones>

00000000004005fc <vListInitialise>:
  4005fc:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400600:	910003fd 	mov	x29, sp
  400604:	f9000fa0 	str	x0, [x29, #24]
  400608:	90000000 	adrp	x0, 400000 <_init-0x480>
  40060c:	91336000 	add	x0, x0, #0xcd8
  400610:	f9400fa1 	ldr	x1, [x29, #24]
  400614:	97ffffb7 	bl	4004f0 <printf@plt>
  400618:	f9400fa0 	ldr	x0, [x29, #24]
  40061c:	f9400401 	ldr	x1, [x0, #8]
  400620:	f9400fa0 	ldr	x0, [x29, #24]
  400624:	91004002 	add	x2, x0, #0x10
  400628:	90000000 	adrp	x0, 400000 <_init-0x480>
  40062c:	9133a000 	add	x0, x0, #0xce8
  400630:	97ffffb0 	bl	4004f0 <printf@plt>
  400634:	f9400fa0 	ldr	x0, [x29, #24]
  400638:	91004001 	add	x1, x0, #0x10
  40063c:	f9400fa0 	ldr	x0, [x29, #24]
  400640:	f9000401 	str	x1, [x0, #8]
  400644:	f9400fa0 	ldr	x0, [x29, #24]
  400648:	f9400401 	ldr	x1, [x0, #8]
  40064c:	f9400fa0 	ldr	x0, [x29, #24]
  400650:	91004002 	add	x2, x0, #0x10
  400654:	90000000 	adrp	x0, 400000 <_init-0x480>
  400658:	9133a000 	add	x0, x0, #0xce8
  40065c:	97ffffa5 	bl	4004f0 <printf@plt>
  400660:	f9400fa0 	ldr	x0, [x29, #24]
  400664:	12800001 	mov	w1, #0xffffffff            	// #-1
  400668:	b9001001 	str	w1, [x0, #16]
  40066c:	f9400fa0 	ldr	x0, [x29, #24]
  400670:	f9400c01 	ldr	x1, [x0, #24]
  400674:	90000000 	adrp	x0, 400000 <_init-0x480>
  400678:	91346000 	add	x0, x0, #0xd18
  40067c:	97ffff9d 	bl	4004f0 <printf@plt>
  400680:	f9400fa0 	ldr	x0, [x29, #24]
  400684:	91004001 	add	x1, x0, #0x10
  400688:	f9400fa0 	ldr	x0, [x29, #24]
  40068c:	f9000c01 	str	x1, [x0, #24]
  400690:	f9400fa0 	ldr	x0, [x29, #24]
  400694:	f9400c01 	ldr	x1, [x0, #24]
  400698:	90000000 	adrp	x0, 400000 <_init-0x480>
  40069c:	91346000 	add	x0, x0, #0xd18
  4006a0:	97ffff94 	bl	4004f0 <printf@plt>
  4006a4:	f9400fa0 	ldr	x0, [x29, #24]
  4006a8:	f9401001 	ldr	x1, [x0, #32]
  4006ac:	90000000 	adrp	x0, 400000 <_init-0x480>
  4006b0:	9134e000 	add	x0, x0, #0xd38
  4006b4:	97ffff8f 	bl	4004f0 <printf@plt>
  4006b8:	f9400fa0 	ldr	x0, [x29, #24]
  4006bc:	91004001 	add	x1, x0, #0x10
  4006c0:	f9400fa0 	ldr	x0, [x29, #24]
  4006c4:	f9001001 	str	x1, [x0, #32]
  4006c8:	f9400fa0 	ldr	x0, [x29, #24]
  4006cc:	f9401001 	ldr	x1, [x0, #32]
  4006d0:	90000000 	adrp	x0, 400000 <_init-0x480>
  4006d4:	9134e000 	add	x0, x0, #0xd38
  4006d8:	97ffff86 	bl	4004f0 <printf@plt>
  4006dc:	f9400fa0 	ldr	x0, [x29, #24]
  4006e0:	f9401000 	ldr	x0, [x0, #32]
  4006e4:	f9400401 	ldr	x1, [x0, #8]
  4006e8:	90000000 	adrp	x0, 400000 <_init-0x480>
  4006ec:	91358000 	add	x0, x0, #0xd60
  4006f0:	97ffff80 	bl	4004f0 <printf@plt>
  4006f4:	f9400fa0 	ldr	x0, [x29, #24]
  4006f8:	f9401000 	ldr	x0, [x0, #32]
  4006fc:	f9400400 	ldr	x0, [x0, #8]
  400700:	f9400401 	ldr	x1, [x0, #8]
  400704:	90000000 	adrp	x0, 400000 <_init-0x480>
  400708:	91364000 	add	x0, x0, #0xd90
  40070c:	97ffff79 	bl	4004f0 <printf@plt>
  400710:	f9400fa0 	ldr	x0, [x29, #24]
  400714:	f9401000 	ldr	x0, [x0, #32]
  400718:	f9400400 	ldr	x0, [x0, #8]
  40071c:	f9400400 	ldr	x0, [x0, #8]
  400720:	f9400401 	ldr	x1, [x0, #8]
  400724:	90000000 	adrp	x0, 400000 <_init-0x480>
  400728:	91372000 	add	x0, x0, #0xdc8
  40072c:	97ffff71 	bl	4004f0 <printf@plt>
  400730:	f9400fa0 	ldr	x0, [x29, #24]
  400734:	f9401000 	ldr	x0, [x0, #32]
  400738:	f9400801 	ldr	x1, [x0, #16]
  40073c:	90000000 	adrp	x0, 400000 <_init-0x480>
  400740:	91382000 	add	x0, x0, #0xe08
  400744:	97ffff6b 	bl	4004f0 <printf@plt>
  400748:	f9400fa0 	ldr	x0, [x29, #24]
  40074c:	f9401000 	ldr	x0, [x0, #32]
  400750:	f9400800 	ldr	x0, [x0, #16]
  400754:	f9400801 	ldr	x1, [x0, #16]
  400758:	90000000 	adrp	x0, 400000 <_init-0x480>
  40075c:	9138e000 	add	x0, x0, #0xe38
  400760:	97ffff64 	bl	4004f0 <printf@plt>
  400764:	f9400fa0 	ldr	x0, [x29, #24]
  400768:	f9401000 	ldr	x0, [x0, #32]
  40076c:	f9400800 	ldr	x0, [x0, #16]
  400770:	f9400800 	ldr	x0, [x0, #16]
  400774:	f9400801 	ldr	x1, [x0, #16]
  400778:	90000000 	adrp	x0, 400000 <_init-0x480>
  40077c:	9139e000 	add	x0, x0, #0xe78
  400780:	97ffff5c 	bl	4004f0 <printf@plt>
  400784:	f9400fa0 	ldr	x0, [x29, #24]
  400788:	f9400c00 	ldr	x0, [x0, #24]
  40078c:	f9400401 	ldr	x1, [x0, #8]
  400790:	90000000 	adrp	x0, 400000 <_init-0x480>
  400794:	913b0000 	add	x0, x0, #0xec0
  400798:	97ffff56 	bl	4004f0 <printf@plt>
  40079c:	f9400fa0 	ldr	x0, [x29, #24]
  4007a0:	f9400c00 	ldr	x0, [x0, #24]
  4007a4:	f9400400 	ldr	x0, [x0, #8]
  4007a8:	f9400401 	ldr	x1, [x0, #8]
  4007ac:	90000000 	adrp	x0, 400000 <_init-0x480>
  4007b0:	913ba000 	add	x0, x0, #0xee8
  4007b4:	97ffff4f 	bl	4004f0 <printf@plt>
  4007b8:	f9400fa0 	ldr	x0, [x29, #24]
  4007bc:	f9400c00 	ldr	x0, [x0, #24]
  4007c0:	f9400400 	ldr	x0, [x0, #8]
  4007c4:	f9400400 	ldr	x0, [x0, #8]
  4007c8:	f9400401 	ldr	x1, [x0, #8]
  4007cc:	90000000 	adrp	x0, 400000 <_init-0x480>
  4007d0:	913c6000 	add	x0, x0, #0xf18
  4007d4:	97ffff47 	bl	4004f0 <printf@plt>
  4007d8:	f9400fa0 	ldr	x0, [x29, #24]
  4007dc:	f9400c00 	ldr	x0, [x0, #24]
  4007e0:	f9400801 	ldr	x1, [x0, #16]
  4007e4:	90000000 	adrp	x0, 400000 <_init-0x480>
  4007e8:	913d4000 	add	x0, x0, #0xf50
  4007ec:	97ffff41 	bl	4004f0 <printf@plt>
  4007f0:	f9400fa0 	ldr	x0, [x29, #24]
  4007f4:	f9400c00 	ldr	x0, [x0, #24]
  4007f8:	f9400800 	ldr	x0, [x0, #16]
  4007fc:	f9400801 	ldr	x1, [x0, #16]
  400800:	90000000 	adrp	x0, 400000 <_init-0x480>
  400804:	913e0000 	add	x0, x0, #0xf80
  400808:	97ffff3a 	bl	4004f0 <printf@plt>
  40080c:	f9400fa0 	ldr	x0, [x29, #24]
  400810:	f9400c00 	ldr	x0, [x0, #24]
  400814:	f9400800 	ldr	x0, [x0, #16]
  400818:	f9400800 	ldr	x0, [x0, #16]
  40081c:	f9400801 	ldr	x1, [x0, #16]
  400820:	90000000 	adrp	x0, 400000 <_init-0x480>
  400824:	913ee000 	add	x0, x0, #0xfb8
  400828:	97ffff32 	bl	4004f0 <printf@plt>
  40082c:	f9400fa0 	ldr	x0, [x29, #24]
  400830:	f9400c00 	ldr	x0, [x0, #24]
  400834:	f9400800 	ldr	x0, [x0, #16]
  400838:	f9400401 	ldr	x1, [x0, #8]
  40083c:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  400840:	91000000 	add	x0, x0, #0x0
  400844:	97ffff2b 	bl	4004f0 <printf@plt>
  400848:	f9400fa0 	ldr	x0, [x29, #24]
  40084c:	f9400c00 	ldr	x0, [x0, #24]
  400850:	f9400800 	ldr	x0, [x0, #16]
  400854:	f9400400 	ldr	x0, [x0, #8]
  400858:	f9400801 	ldr	x1, [x0, #16]
  40085c:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  400860:	9100e000 	add	x0, x0, #0x38
  400864:	97ffff23 	bl	4004f0 <printf@plt>
  400868:	f9400fa0 	ldr	x0, [x29, #24]
  40086c:	f9401000 	ldr	x0, [x0, #32]
  400870:	f9400400 	ldr	x0, [x0, #8]
  400874:	f9400801 	ldr	x1, [x0, #16]
  400878:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  40087c:	9101e000 	add	x0, x0, #0x78
  400880:	97ffff1c 	bl	4004f0 <printf@plt>
  400884:	f9400fa0 	ldr	x0, [x29, #24]
  400888:	f9401000 	ldr	x0, [x0, #32]
  40088c:	f9400400 	ldr	x0, [x0, #8]
  400890:	f9400800 	ldr	x0, [x0, #16]
  400894:	f9400401 	ldr	x1, [x0, #8]
  400898:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  40089c:	9102c000 	add	x0, x0, #0xb0
  4008a0:	97ffff14 	bl	4004f0 <printf@plt>
  4008a4:	f9400fa0 	ldr	x0, [x29, #24]
  4008a8:	f900001f 	str	xzr, [x0]
  4008ac:	d503201f 	nop
  4008b0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4008b4:	d65f03c0 	ret

00000000004008b8 <vListInsertEnd>:
  4008b8:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4008bc:	910003fd 	mov	x29, sp
  4008c0:	f9000fa0 	str	x0, [x29, #24]
  4008c4:	f9000ba1 	str	x1, [x29, #16]
  4008c8:	f9400fa0 	ldr	x0, [x29, #24]
  4008cc:	f9400400 	ldr	x0, [x0, #8]
  4008d0:	f90017a0 	str	x0, [x29, #40]
  4008d4:	f9400fa0 	ldr	x0, [x29, #24]
  4008d8:	f9400401 	ldr	x1, [x0, #8]
  4008dc:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  4008e0:	9103c000 	add	x0, x0, #0xf0
  4008e4:	f9400ba3 	ldr	x3, [x29, #16]
  4008e8:	aa0103e2 	mov	x2, x1
  4008ec:	f94017a1 	ldr	x1, [x29, #40]
  4008f0:	97ffff00 	bl	4004f0 <printf@plt>
  4008f4:	f9400ba0 	ldr	x0, [x29, #16]
  4008f8:	f9400401 	ldr	x1, [x0, #8]
  4008fc:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  400900:	9104a000 	add	x0, x0, #0x128
  400904:	97fffefb 	bl	4004f0 <printf@plt>
  400908:	f9400ba0 	ldr	x0, [x29, #16]
  40090c:	f94017a1 	ldr	x1, [x29, #40]
  400910:	f9000401 	str	x1, [x0, #8]
  400914:	f9400ba0 	ldr	x0, [x29, #16]
  400918:	f9400401 	ldr	x1, [x0, #8]
  40091c:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  400920:	91052000 	add	x0, x0, #0x148
  400924:	f94017a2 	ldr	x2, [x29, #40]
  400928:	97fffef2 	bl	4004f0 <printf@plt>
  40092c:	f9400ba0 	ldr	x0, [x29, #16]
  400930:	f9400801 	ldr	x1, [x0, #16]
  400934:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  400938:	9105e000 	add	x0, x0, #0x178
  40093c:	97fffeed 	bl	4004f0 <printf@plt>
  400940:	f94017a0 	ldr	x0, [x29, #40]
  400944:	f9400801 	ldr	x1, [x0, #16]
  400948:	f9400ba0 	ldr	x0, [x29, #16]
  40094c:	f9000801 	str	x1, [x0, #16]
  400950:	f9400ba0 	ldr	x0, [x29, #16]
  400954:	f9400801 	ldr	x1, [x0, #16]
  400958:	f94017a0 	ldr	x0, [x29, #40]
  40095c:	f9400802 	ldr	x2, [x0, #16]
  400960:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  400964:	91066000 	add	x0, x0, #0x198
  400968:	97fffee2 	bl	4004f0 <printf@plt>
  40096c:	f94017a0 	ldr	x0, [x29, #40]
  400970:	f9400800 	ldr	x0, [x0, #16]
  400974:	f9400401 	ldr	x1, [x0, #8]
  400978:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  40097c:	91076000 	add	x0, x0, #0x1d8
  400980:	97fffedc 	bl	4004f0 <printf@plt>
  400984:	f94017a0 	ldr	x0, [x29, #40]
  400988:	f9400800 	ldr	x0, [x0, #16]
  40098c:	f9400ba1 	ldr	x1, [x29, #16]
  400990:	f9000401 	str	x1, [x0, #8]
  400994:	f94017a0 	ldr	x0, [x29, #40]
  400998:	f9400800 	ldr	x0, [x0, #16]
  40099c:	f9400401 	ldr	x1, [x0, #8]
  4009a0:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  4009a4:	91076000 	add	x0, x0, #0x1d8
  4009a8:	97fffed2 	bl	4004f0 <printf@plt>
  4009ac:	f94017a0 	ldr	x0, [x29, #40]
  4009b0:	f9400801 	ldr	x1, [x0, #16]
  4009b4:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  4009b8:	91080000 	add	x0, x0, #0x200
  4009bc:	97fffecd 	bl	4004f0 <printf@plt>
  4009c0:	f94017a0 	ldr	x0, [x29, #40]
  4009c4:	f9400ba1 	ldr	x1, [x29, #16]
  4009c8:	f9000801 	str	x1, [x0, #16]
  4009cc:	f94017a0 	ldr	x0, [x29, #40]
  4009d0:	f9400801 	ldr	x1, [x0, #16]
  4009d4:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  4009d8:	91088000 	add	x0, x0, #0x220
  4009dc:	97fffec5 	bl	4004f0 <printf@plt>
  4009e0:	f9400ba0 	ldr	x0, [x29, #16]
  4009e4:	f9400fa1 	ldr	x1, [x29, #24]
  4009e8:	f9001001 	str	x1, [x0, #32]
  4009ec:	f9400fa0 	ldr	x0, [x29, #24]
  4009f0:	f9400000 	ldr	x0, [x0]
  4009f4:	91000401 	add	x1, x0, #0x1
  4009f8:	f9400fa0 	ldr	x0, [x29, #24]
  4009fc:	f9000001 	str	x1, [x0]
  400a00:	d503201f 	nop
  400a04:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400a08:	d65f03c0 	ret

0000000000400a0c <vListInsert>:
  400a0c:	d10083ff 	sub	sp, sp, #0x20
  400a10:	f90007e0 	str	x0, [sp, #8]
  400a14:	f90003e1 	str	x1, [sp]
  400a18:	f94003e0 	ldr	x0, [sp]
  400a1c:	b9400000 	ldr	w0, [x0]
  400a20:	b90017e0 	str	w0, [sp, #20]
  400a24:	b94017e0 	ldr	w0, [sp, #20]
  400a28:	3100041f 	cmn	w0, #0x1
  400a2c:	540000a1 	b.ne	400a40 <vListInsert+0x34>  // b.any
  400a30:	f94007e0 	ldr	x0, [sp, #8]
  400a34:	f9401000 	ldr	x0, [x0, #32]
  400a38:	f9000fe0 	str	x0, [sp, #24]
  400a3c:	1400000e 	b	400a74 <vListInsert+0x68>
  400a40:	f94007e0 	ldr	x0, [sp, #8]
  400a44:	91004000 	add	x0, x0, #0x10
  400a48:	f9000fe0 	str	x0, [sp, #24]
  400a4c:	14000004 	b	400a5c <vListInsert+0x50>
  400a50:	f9400fe0 	ldr	x0, [sp, #24]
  400a54:	f9400400 	ldr	x0, [x0, #8]
  400a58:	f9000fe0 	str	x0, [sp, #24]
  400a5c:	f9400fe0 	ldr	x0, [sp, #24]
  400a60:	f9400400 	ldr	x0, [x0, #8]
  400a64:	b9400000 	ldr	w0, [x0]
  400a68:	b94017e1 	ldr	w1, [sp, #20]
  400a6c:	6b00003f 	cmp	w1, w0
  400a70:	54ffff02 	b.cs	400a50 <vListInsert+0x44>  // b.hs, b.nlast
  400a74:	f9400fe0 	ldr	x0, [sp, #24]
  400a78:	f9400401 	ldr	x1, [x0, #8]
  400a7c:	f94003e0 	ldr	x0, [sp]
  400a80:	f9000401 	str	x1, [x0, #8]
  400a84:	f94003e0 	ldr	x0, [sp]
  400a88:	f9400400 	ldr	x0, [x0, #8]
  400a8c:	f94003e1 	ldr	x1, [sp]
  400a90:	f9000801 	str	x1, [x0, #16]
  400a94:	f94003e0 	ldr	x0, [sp]
  400a98:	f9400fe1 	ldr	x1, [sp, #24]
  400a9c:	f9000801 	str	x1, [x0, #16]
  400aa0:	f9400fe0 	ldr	x0, [sp, #24]
  400aa4:	f94003e1 	ldr	x1, [sp]
  400aa8:	f9000401 	str	x1, [x0, #8]
  400aac:	f94003e0 	ldr	x0, [sp]
  400ab0:	f94007e1 	ldr	x1, [sp, #8]
  400ab4:	f9001001 	str	x1, [x0, #32]
  400ab8:	f94007e0 	ldr	x0, [sp, #8]
  400abc:	f9400000 	ldr	x0, [x0]
  400ac0:	91000401 	add	x1, x0, #0x1
  400ac4:	f94007e0 	ldr	x0, [sp, #8]
  400ac8:	f9000001 	str	x1, [x0]
  400acc:	d503201f 	nop
  400ad0:	910083ff 	add	sp, sp, #0x20
  400ad4:	d65f03c0 	ret

0000000000400ad8 <uxListRemove>:
  400ad8:	d10083ff 	sub	sp, sp, #0x20
  400adc:	f90007e0 	str	x0, [sp, #8]
  400ae0:	f94007e0 	ldr	x0, [sp, #8]
  400ae4:	f9401000 	ldr	x0, [x0, #32]
  400ae8:	f9000fe0 	str	x0, [sp, #24]
  400aec:	f94007e0 	ldr	x0, [sp, #8]
  400af0:	f9400400 	ldr	x0, [x0, #8]
  400af4:	f94007e1 	ldr	x1, [sp, #8]
  400af8:	f9400821 	ldr	x1, [x1, #16]
  400afc:	f9000801 	str	x1, [x0, #16]
  400b00:	f94007e0 	ldr	x0, [sp, #8]
  400b04:	f9400800 	ldr	x0, [x0, #16]
  400b08:	f94007e1 	ldr	x1, [sp, #8]
  400b0c:	f9400421 	ldr	x1, [x1, #8]
  400b10:	f9000401 	str	x1, [x0, #8]
  400b14:	f9400fe0 	ldr	x0, [sp, #24]
  400b18:	f9400400 	ldr	x0, [x0, #8]
  400b1c:	f94007e1 	ldr	x1, [sp, #8]
  400b20:	eb00003f 	cmp	x1, x0
  400b24:	540000a1 	b.ne	400b38 <uxListRemove+0x60>  // b.any
  400b28:	f94007e0 	ldr	x0, [sp, #8]
  400b2c:	f9400801 	ldr	x1, [x0, #16]
  400b30:	f9400fe0 	ldr	x0, [sp, #24]
  400b34:	f9000401 	str	x1, [x0, #8]
  400b38:	f94007e0 	ldr	x0, [sp, #8]
  400b3c:	f900101f 	str	xzr, [x0, #32]
  400b40:	f9400fe0 	ldr	x0, [sp, #24]
  400b44:	f9400000 	ldr	x0, [x0]
  400b48:	d1000401 	sub	x1, x0, #0x1
  400b4c:	f9400fe0 	ldr	x0, [sp, #24]
  400b50:	f9000001 	str	x1, [x0]
  400b54:	f9400fe0 	ldr	x0, [sp, #24]
  400b58:	f9400000 	ldr	x0, [x0]
  400b5c:	910083ff 	add	sp, sp, #0x20
  400b60:	d65f03c0 	ret

0000000000400b64 <main>:
  400b64:	a9b47bfd 	stp	x29, x30, [sp, #-192]!
  400b68:	910003fd 	mov	x29, sp
  400b6c:	a9097fbf 	stp	xzr, xzr, [x29, #144]
  400b70:	a90a7fbf 	stp	xzr, xzr, [x29, #160]
  400b74:	f9005bbf 	str	xzr, [x29, #176]
  400b78:	a906ffbf 	stp	xzr, xzr, [x29, #104]
  400b7c:	a907ffbf 	stp	xzr, xzr, [x29, #120]
  400b80:	f90047bf 	str	xzr, [x29, #136]
  400b84:	52800f60 	mov	w0, #0x7b                  	// #123
  400b88:	b9006ba0 	str	w0, [x29, #104]
  400b8c:	a9047fbf 	stp	xzr, xzr, [x29, #64]
  400b90:	a9057fbf 	stp	xzr, xzr, [x29, #80]
  400b94:	f90033bf 	str	xzr, [x29, #96]
  400b98:	52803900 	mov	w0, #0x1c8                 	// #456
  400b9c:	b90043a0 	str	w0, [x29, #64]
  400ba0:	a901ffbf 	stp	xzr, xzr, [x29, #24]
  400ba4:	a902ffbf 	stp	xzr, xzr, [x29, #40]
  400ba8:	f9001fbf 	str	xzr, [x29, #56]
  400bac:	528062a0 	mov	w0, #0x315                 	// #789
  400bb0:	b9001ba0 	str	w0, [x29, #24]
  400bb4:	910063a4 	add	x4, x29, #0x18
  400bb8:	910103a3 	add	x3, x29, #0x40
  400bbc:	9101a3a2 	add	x2, x29, #0x68
  400bc0:	910243a1 	add	x1, x29, #0x90
  400bc4:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0x340>
  400bc8:	91090000 	add	x0, x0, #0x240
  400bcc:	97fffe49 	bl	4004f0 <printf@plt>
  400bd0:	910243a0 	add	x0, x29, #0x90
  400bd4:	f9005fa0 	str	x0, [x29, #184]
  400bd8:	910243a0 	add	x0, x29, #0x90
  400bdc:	97fffe88 	bl	4005fc <vListInitialise>
  400be0:	9101a3a0 	add	x0, x29, #0x68
  400be4:	aa0003e1 	mov	x1, x0
  400be8:	f9405fa0 	ldr	x0, [x29, #184]
  400bec:	97ffff33 	bl	4008b8 <vListInsertEnd>
  400bf0:	910103a0 	add	x0, x29, #0x40
  400bf4:	aa0003e1 	mov	x1, x0
  400bf8:	f9405fa0 	ldr	x0, [x29, #184]
  400bfc:	97ffff2f 	bl	4008b8 <vListInsertEnd>
  400c00:	910063a0 	add	x0, x29, #0x18
  400c04:	aa0003e1 	mov	x1, x0
  400c08:	f9405fa0 	ldr	x0, [x29, #184]
  400c0c:	97ffff2b 	bl	4008b8 <vListInsertEnd>
  400c10:	910103a0 	add	x0, x29, #0x40
  400c14:	97ffffb1 	bl	400ad8 <uxListRemove>
  400c18:	d503201f 	nop
  400c1c:	a8cc7bfd 	ldp	x29, x30, [sp], #192
  400c20:	d65f03c0 	ret
  400c24:	00000000 	.inst	0x00000000 ; undefined

0000000000400c28 <__libc_csu_init>:
  400c28:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400c2c:	910003fd 	mov	x29, sp
  400c30:	a901d7f4 	stp	x20, x21, [sp, #24]
  400c34:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0xfd94>
  400c38:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0xfd94>
  400c3c:	91374294 	add	x20, x20, #0xdd0
  400c40:	913722b5 	add	x21, x21, #0xdc8
  400c44:	a902dff6 	stp	x22, x23, [sp, #40]
  400c48:	cb150294 	sub	x20, x20, x21
  400c4c:	f9001ff8 	str	x24, [sp, #56]
  400c50:	2a0003f6 	mov	w22, w0
  400c54:	aa0103f7 	mov	x23, x1
  400c58:	9343fe94 	asr	x20, x20, #3
  400c5c:	aa0203f8 	mov	x24, x2
  400c60:	97fffe08 	bl	400480 <_init>
  400c64:	b4000194 	cbz	x20, 400c94 <__libc_csu_init+0x6c>
  400c68:	f9000bb3 	str	x19, [x29, #16]
  400c6c:	d2800013 	mov	x19, #0x0                   	// #0
  400c70:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400c74:	aa1803e2 	mov	x2, x24
  400c78:	aa1703e1 	mov	x1, x23
  400c7c:	2a1603e0 	mov	w0, w22
  400c80:	91000673 	add	x19, x19, #0x1
  400c84:	d63f0060 	blr	x3
  400c88:	eb13029f 	cmp	x20, x19
  400c8c:	54ffff21 	b.ne	400c70 <__libc_csu_init+0x48>  // b.any
  400c90:	f9400bb3 	ldr	x19, [x29, #16]
  400c94:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400c98:	a942dff6 	ldp	x22, x23, [sp, #40]
  400c9c:	f9401ff8 	ldr	x24, [sp, #56]
  400ca0:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400ca4:	d65f03c0 	ret

0000000000400ca8 <__libc_csu_fini>:
  400ca8:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400cac <_fini>:
  400cac:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400cb0:	910003fd 	mov	x29, sp
  400cb4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400cb8:	d65f03c0 	ret
